
A generic introduction to simulation "cases" in the dotools.



A "case" is a set of fet models, operating temperature, and supply
voltage with which we want to be able to run simulations.  The idea is
to be able to easily change to a different set of these parameters and
rerun a simulation to see how a circuit performs under various
circumstances that might be encountered when the chip is actually fabricated.

Any combination of parameter values can be collected into a named case
for easy reference, but here are the ones that we find to be most
important for verifying that a CMOS circuit is suitably robust.

A cases file consists of one line per case, with three or four
whitespace-seperate columns, casename, Vdd, tepmerature, and optionaly
modelname.

example:
N       2.5     85
W       2.25    110
B       2.75    25
NLH	2.25	110	N


If the fourth column, modelfile, is not present, the modelfile name is
the same as the case name.    In the example above, the case named
NLH combines "N" models, low voltage, and high temperature.   

Starting with dtools release 20020124, additional name=value parameters
may be specified on a cases-file line, in this style:

B       2.75    25		 _resmodel_=B.res _paramfile_=B.param _ivdd_supply_=5.0
NLH	2.25	110	N	 _resmodel_=N.res _paramfile_=N.param

Each additional name=value parameters is equivalent to specifying
"--define name=value" on the dospice command line.  These definitions
can be substituted into spice-deck templates, command files and load
files by spicepp.  Note that model files and the netlist file do not
get processed by spicepp.  Case-file definitions and their values may
not contain whitespace nor equal signs.

All of these parameters may be overridden with --define name=value on
the command line.

By tradition, we surround parameter names with one or more underscores
(i.e. _resmodel_, __case__) to reduce the likelyhood of name
collisions with spice deck netnames or device model names.

By convention we choose one or two capital letters to name each case,
but any string could be used.  Since the case name becomes part of
many filenames that users must type, it is worth sticking to the
shortest names possible.  Case names should not incorporate the name
of a fab vendor or technology generation.



N - "Nominal"

Everything at nominal values.  Models for the expected average
transistor parameters, supply voltage at the nominal stated value, say
3.3v, and die temperature at a typical operating level, often 85
degrees C.

B - "Best"

The combination of parameters that gives the fastest complementary
logic performance.  Highest allowable supply voltage, 5 or 10% above
nominal.  Lowest temperature.  Fastest permissible transistors,
usually taken from the manufacturer's 3 or 6 sigma process point data.

W - "Worst"

Combination for slowest logic performance.  Low voltage and high
temperature.  Slowest transistor models.

NN - "Noisy Nfet"
Weakest or noisiest NFET with strongest pfet that can occur on one die.
Usually at maximum voltage and minimum temperature.   Note that this is not
the same as taking the nfets from W and pfets from B, because some 
fabrication varations affect nfets and pfets equally (like oxide thickness)
while others are largely independent.

NP - "noisy Pfet"
Weakest or noisiest PFET, strongest nfet that can occur together on the
same die.  Usually at minimum voltage and maximum temperature.


NN and NP should result in the two extremes of nfet-pfet mismatch, for
example as evidenced by variations in inverter switching threshold
(Vinv).  Simulating at both of these is important for any circuit
where an nfet is balanced against a pfet, for example in a CMOS memory
cell or anything else with cross-coupled inverters.


M - metal migration
This case is the worst-case for metal migration, usually combining best-case
(maxmium current) transistors with highest temperature.




If you only have typical-case transistor models, you can make a guess
at fast and slow model parameters to use in assembling the B and W
cases.  Here are some guidelines, using the level3 parameters:

To get an approximate best case from nominal case:
Decrease TOX (oxide thickness) by 2-3% 2.5%
Increase U0 (mobility) by 3 to 6%
Decrease VT0 (threshold voltage) by 10%
Increase LD (lateral diffusion distance) by 60-75%
Decrease CGDO, CGSO, CJ, CJSW (capacitances) by 10%
Decrease RSH (diffusion sheet resistance) by 50%

To get a plausible approximation to worst case from nominal case:
Increase TOX (oxide thickness) by 1.5-2%
Decrease U0 (mobility) by 3 to 6%
Increase VT0 (threshold voltage) by 10%
Decrease LD (lateral diffusion distance) by 60-75%
Increase CGDO, CGSO, CJ, CJSW (capacitances) by 10%
Increase RSH (diffusion sheet resistance) by 150%

(These numbers were all obtained by comparing the various cases of the
the fake0.35 models; they should be compared against some other
models)



