

An outline of VLSI design flow with the "do" tools.

Steve Tell, January 15, 1996

Develop high-level specification for circuit or chip to be designed
This has been done in verilog and in a particular style of C++

Lay out the logic in magic.  This may include hand-painted transistors and
standard-cell layouts done by hand or with oasis.  We've also done some logic
synthesis with Cadence's Synergy, and then fed the netlist of standard cells
into the Oasis place & route tool.

Specify input and output characteristics for circuit.  These specifications
include the timing characteristics and and which edge the signal is to be
generated (for inputs ) or sampled (for outputs) on.
These specifications go in the header section of our test vector file format.

Develop test vectors for the circuit.  Usually this is done by instrumenting
the high-level executable specification (verilog or C++).  Currently, the
tools can only handle synchronous circuits which are active on the high,
low, or both clock edges.
Vectors consist of a file with a header section and then a body with
one line per clock edge, specifying inputs and outputs.

Run the test vectors against the circuit in the irsim switch level simulator.
The doirsim program makes this lots easier:
	- converts standard vector format into irsim command input
	- concatenates one or more .sim files together
	- runs .sim files through 'irprep' prefilter and some other filters
	  For example, transistors with the "Sim:Nil" gate attribute are
	  deleted, and all nodes named "GND_whatever" can connected to the
	  global GND when simulating a subcell instead of a whole chip.
	- runs the simulator
	- converts irsim output back into one-line-per-cycle format
	- compares actual circuit outputs with expected values in test vectors
	- if the vectors don't match, designer can look at the actual and
	expected output, or dive into irsim itself with a variation that
	runs simulation until a breakpoint, and then leaves you in irsim
	interactive command line mode.

Run the test vectors against the circuit with the CAzM or HSPICE analog
simulators.
The docazm and dohspice programs make this lots easier:
	- converts standard vector format into cazm or hspice command input,
	  converting digital input vectors into piecewise-linear analog form
	  with appropriate timing and wave shape.
	  Waveforms are stored versions of actual output from a typical
	  flip-flop, interpolated from waveforms sampled at various
	  fanouts.
	- Selects the right combination of transistor model, temperature,
	  Vdd voltage, and input waveform shapes for the specified "case".
	  Typical, cases include "Best," (fast) "Worst," (slow) "Nominal,"
	  "Worst-case Metal Migration," some additional process corners, etc.
	- appends a "loads" file to the circuit deck.  In the loads file,
	  the designer specifies typical circuits to be driven by the circuit
	  under test.  This may be a simple capacitive load, 
	  an RC ladder, or somthing more complex.  Format for the .loads file
	  is like spice netlist, but with some additional metacommands.
	- runs the analog simulator
	- samples the output waveforms at clock edges, producing digital
	  output vectors.  Flags setup-time violations based on timing spec.
	- compares actual circuit outputs with expected values in test vectors

	- if all test vectors don't match, you can look at the vectors or the
	actuall output waveforms.  Currently, we use sigview for cazm
	output, but would like somthing better.

Docazm only adds these options:
	- measurement of overall circuit power consumption waveform.
	- measurement of current waveforms from a circuit's output into
	  its load circuit.  Generates report, including minimum recommended
	  wire size for each output.

Run additional design-rule checks on the cell.  (Generally these are run
on cells to go in a library or on complete chips only)






