

NAME	
	doverilog - stimulate and test a verilog design with .in file vectors

SYNOPSIS

 doverilog [options] rootname extra-verilog-files ...
options:
  -C|--clock name              rename main clock signal from default Clk
  -D|--debug                   leaves temp files, and other debugging stuff.
  -l|--logfile                 write log to specified file
  -n|--norun                   print commands only, don't do anything
  --nopli                      create testbench without using PLI vector reader
  --a|analyzer a               dump waveforms in type a; a is vcd, shm, etc.
  --period p                   set period in verilog ticks
  --powernets                  Connect power ports VDD and GND to verilog DUT
  --rootmodule  name           test named verilog module instead of rootname
  --define defstr              pass +define+defstr to verilog
  -t|--testcase testcase-name  use rootname.testcase.in, etc.
  -v|--verbose
  --verilog name               name of the verilog simulator to use
  -V|--vlopt  A                pass single argument A directly to simulator
                               A cannot contain spaces.

DESCRIPTION

Doverilog constructs a testbench and runs a verilog simulation.
Stimuli and expected results come from a .in file; see infile(5) for generic
.in file info.

Trivial .in files "just work" for testing modules that do not uses
bus ports or inout ports.

To handle inout ports, declare the signal in both the "inputs:"
and "outputs:" section.  Use 'z' in the input column when the testbench
should not be driving the signal.


Bus ports present some difficulty.  Bus port inputs must correspond
exactly to a single line in the "inputs:" section and a single field
in the vectors section.  In addition, the "vport" attribute must be used to
specifiy the name of the verilog port:

inputs:
iBus[{1:0}] vport=iBus

Outputs are typicaly handled by heirarchical reference, but if the use
of the port is desired, specify a vport attribute as well.



Some setups cannot be handled in doverilog's testbench generator.
One such thing is differential clocks, or any clocking other than one cycle
per vector (or vector pair, when using double-edged vectors).

In this case, build a wrapper around your DUT, and use this wrapper as
doverilog's root module (with --rootmodule).  Inside the wrapper, map
doverilog's one clock signal into the required clocks.

Other things typicaly done in a wrapper are adding pullups to
open-drain outputs.


FUTURE WORK

Extend this preliminary document and convert it to docbook/refentry format.

SEE ALSO

infile(5)
doirsim(1)
dospice(1)

