
Setting up the DoTools for a new technology

1. If you haven't already done so, create a suitable magic technolgy
file and extract section.  It is quite likely that an existing
techfile will work if a suitable extract section is written.  Doing
this will require the fab vendor's information on geometric design
rules and parasitic capacitances.

2. Set up an appropriately-named subdirectory of share/cmos-models to
contain the spice models and related stuff.

Get the spice models from your fab vendor.  This may require signing a
non-disclosure agreement.  Somtimes models are available from Mosis.
Reformat them as necessary to create individual files for each case.
Sometimes a set of models will be distributed as a single file with
.LIB/.ENDL delimiting seperate spice "libraries" within the file.  The
spicelibsplit script can help break these into seperate files.  If you
only have one model file, it is probably for the "nominal" fabrication
parameters.

Caution: carriage return characters (control-M) will cause HSPICE to
go into an infinite loop reading your model files.  Be sure to check
to see if your model files have been mangled by an MS-DOS system,
and remove CRs if so.

(describe how to approximate other cases by tweaking parameters such as
Tox, Vth, capacitances, etc. from the nominal values)

Write the "cases" file containing the table of cases, using the
supplied one as a guide.  Only list the cases for which you actually
have model files.

Write the "techstyle" file containing the list of magic
technolgy/extract style pairs that the models will work with.

Dospice will now run, but all it can do for you is select the
appropriate supply voltage, temperature, and model from the simulation
case that you specify.  A little more work is required before you can
use its most powerful features, namely simulated clock and data waveforms,
and digital test-vector conversion.

3. Set up an appropriately-named subdirectory of share/dotools to
contain the the waveform templates.

Copy the setup directory and all of its files from the
$prefix/share/dotools/waves-setup directory to some other directory,
perhaps named setup_my-technology.  The dotools-waves-setup
directory is configured to build the waveforms 
using the supplied level 3 models for the hpcmos14 technology.

As of this writing, the Makefile in setup assumes that you'll be using
HSPICE.  If using another spice, some filenames may need to be
changed; for example the raw waveform output files may not be called
*.tr0.

3.1. Edit the Makefile in setup_my-technology, to set these makefile variables:
	models = pathname where you put the spice models
	waves = pathname where wave files will be installed 
	Period = clock period to use for wave generation
	Minlength = minimum fet gate length in your technology
	Lambda = lambda for extracting magic layout for this technology

Further comments in the makefile describe each of these variables.
	
3.2. First, generate the clock waveforms for each case.  ckbuf.ufa is a
spice deck for a parameterizable tapered-inverter-buffer clock generator.
Run this command to build all of the clock waveforms:
	gmake clocks
Confirm that the files Clock.N, Clock.B, Clock.W, etc. get generated.

3.3. If desired, run this command to compare the original clock buffer output
against the sampled waveform template in Clock.N:
	gmake ckbuf.test.N.tr0
Examine ckbuf.test.N.tr0 with your favorite waveform viewer.  Run the other
ckbuf.test.*.tr0 cases if desired. 

The .param statements in ckbuf.ufa can be edited to tune the clock buffer to
your needs.  Often when running at higher speeds, the clock buffer's fanout
needs to be reduced; this is done with the "fan" parameter.  Alternately 
you can substitute a whole new clock buffer circuit for use in generating
waveforms.

3.4. Generate the ETFO parameter files for each type of flip-flop.  The
spice deck ff.ufa is a parameterizable model of a "strong-arm latch,"
a robust differential-input edge-triggered flip-flop modeled after a
paper by the designers of the StrongArm microprocessor.  The command
	gmake ffwaves
will simulate this circuit and to various postprocessing
to create the petff.N, petff.B, etc. waveform template files.

3.5. If desired, run commands like "gmake ff.test.N.tr0" to simulate
both the original flip-flop circuit and the waveforms reconstructed
from the petff.* template files.  Compare them using a waveform viewer.


4. If using the wire-size checker (which is broken at the mement)
write the table of wire-sizing rules.  Based on the fab vendor's
proprietary design rules.

5. In order to use doirsim, generate the irsim.prm file that controls
irsim's simplistic strength and timing model, and copy it to
share/cmos-models.  See the irsim documentation.

