"! considered harmful"

A case for not using global nodes in magic.

The classic Magic VLSI layout editor, originaly from Berkeley,
provides a mechanisim for identifiying global nets, such as power
supplies.  If you label a node "Vdd!" it is considered global, and
implicitly connected to all other nodes labeled "Vdd!".  Instead of
being subject to the usual hierarchical netlist processing, these nodes
simply appears as "Vdd!" in netlists generated by ext2spice, ext2sim, and
derivatives.

We believe that this is the wrong mechanism for handling global power
nodes, and we think we have a better one.  This was partialy inspired
by secondhand information about a fab run of $50,000 worth of silicon
souvenirs, discarded because the power wiring was incomplete.

The problem is not global nodes per se, but rather the level at which
they are handled.  Frequently a subcell will have multiple power,
ground, and clock terminals that are to be connected together with
metal at the next level up in the cell heirarchy.  It is important to
be able to extract and simulate these subcells without necessarily
wiring up the whole chip around them.

Suppose you've got a cell, say ff.mag, with two horizontal metal2
ground rails.  Magic's solution would have you label those metal2
rails "GND!."  Extract ff.mag, into a netlist where the ground node is
GND!, and simulate. All is well.  Now instantiate a bunch of ff's, and
connect them together.  Build up the and simulate rest of the chip in
a similar manner.  But suppose that you forgot to add metal to connect
one of the ground rails in one ff.mag to the chip's ground wiring
network.  Your full-chip netlist will simply have one GND! node, and
will simulate fine.  But that cell has a floating node instead of ground
ground, and your chip won't work.

The problem with doing global-node merging in the netlister is that
information is being thrown away, information that could have been used
to detect this error before taping out the chip.

Our solution is to avoid the "!" global mechanism alltogether.  We
require that only conductors that are actually connected together
within a cell have the same label, and immediately resolve magic's
extractor-time feedback about duplicate nodnames.  Nodes that are to
be connected together at a higher level must be given different names,
according to the following scheme: label at most one such node with the
original name, for example "GND."  Label the others GND_1, GND_2, etc.
Similar for Vdd, Vdd_1, Clk, Clk_1, etc.

Now, the extracted netlist accurately reflects what is in the actual
metalization of the chip or subcell.  In order to simulate subcells,
we run the .sim file or .fa (spice netlist) file through a tool call
subglobs.  Subglobs is given a list of global node base names that
have been chosen for a project, usually "GND," "Vdd," and "Clk."  All
nodesnames matching these patterns are folded to the base name by
stripping off any heirarchical prefix and numbered _N suffix.  This
produces a netlist suitable for simulation.  Subglobs also prints out
a list of all of the nodenames that it has merged together. We wrap
all of our simulators in scripts that run subglobs as well as doing
other checks and preparation.

When it comes time to netlist a whole chip, we do not apply subglobs
to the simulation netlist: the metal connections should merge together
all of the nodes like /sub/cell/GND_1 into the top-level GND node.
Instead we apply subglobs to a dummy copy of the netlist, and verify
that it doesn't find any such nodes to merge.  If it does, the
nodename printed contains the exact heirarchical path to the cell that
needs to be fixed.

A slight variation is to label at the top level all of a chip's
multiple ground and power pads with GND_padnumber and Vdd_padnumber.
Then compare the output from the full-chip subglobs run with a known
list of GND and Vdd pads.  This verifies that all of the GND and Vdd
pads are connected to the global power metalization, as well as
flushing out any of the problems described above. 


